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ds07-13740-1e fujitsu semiconductor data sheet 16-bit proprietary microcontroller cmos f 2 mc-16lx mb90378 series mb90f378/v378 description the mb90378 series is a line of general-purpose, 16-bit microcontrollers designed for those applications which require high-speed real-time processing. the instruction se t is designed to be optimized for controller applications which inheriting the at architecture of f 2 mc-16lx family and allow a wide range of control tasks to be processed efficiently at high speed. a built-in lpc interface, serial irq and ps/2 interface simplifies communication with host cpu and ps/2 devices in computer system. moreover, smbus compliant i 2 c* 2 and a/d converter implements the smart battery control. with these features, the mb90378 series matches itself as keyboard controller with smart battery control. while inheriting the at architecture of the f 2 mc* 1 family, the instruction set for the f 2 mc-16lx cpu core of the mb90378 series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, the mb90378 series has an on-chi p 32-bit accumulator which enables processing of long-word data. *1 : f 2 mc stands for fujitsu flexible microcontrolle r, a registered tradema rk of fujitsu limited. *2 : purchase of fujitsu i 2 c components conveys a license under the philips i 2 c patent rights to use, these components in an i 2 c system provided that the system conforms to the i 2 c standard specification as defined by philips. pac k ag e 144-pin plastic lqfp (fpt-144p-m12)
mb90378 series 2 features ? clock ? embedded pll clock multiplication circuit operating clock (pll clock) can selected from divided-by -2 of oscillation or one to four times the oscillation (at oscillation of 4 mhz to 20 mhz) minimum instruction execution time of 50 ns (at oscillation of 5 mhz, f our times the pll clock, operation at v cc of 3.3 v) ? cpu addressing space of 16 mbytes internal 24-bit addressing ? instruction set optimized for controller applications rich data types (bit, byte, word, long word) rich addressing mode (23 types) high code efficiency enhanced precision calculation realized by the 32-bit accumulator ? instruction set designed for high leve l language (c) and multi-task operations adoption of system stack pointer enhanced pointer indirect instructions barrel shift instructions ? program patch function (2 address pointer) ? improved execution speed 4-byte instruction queue ? powerful interrupt function priority level programmable : 8 levels 32 factors of stronger interrupt function ? automatic data transmission func tion independent of cpu operation extended intelligent i/o service function (ei 2 os) maximum 16 channels ? low-power consumption (standby) mode sleep mode (mode in which cpu operating clock is stopped) timebase timer mode (mode in which operations ot her than timebase timer and watch timer are stopped) stop mode (mode in which all oscillations are stopped) cpu intermittent operation mode watch mode ? dual operation flash upper and lower banks of flash memory can be used to execute er ase/program and read operation concurrently (mb90f378) ? package lqfp-144 (fpt-144p-m12 : 0.4 mm pitch) ? process cmos technology
mb90378 series 3 product lineup (continued) part number parameter mb90f378 mb90v378 classification flash type rom ? rom size 128 kbytes (112 kbytes + 16 kbytes) dual operation ? ram size 6 kbytes 15.6 kbytes cpu function number of instruction : 351 minimum execution time : 50 ns/5 mhz (pll x 4) addressing mode : 23 data bit length : 1, 8, 16 bits maximum memory space : 16 mbytes i/o port i/o port (nch) : 25 i/o port (cmos) : 68 i/o port (cmos with pull-up control) : 32 total : 125 16-bit reload timer reload timer : 6 channels reload mode, single-shot mode or event count mode selectable 8/16-bit ppg timer ppg timer : 2 channels (8-bit mode, 4 channels) 16-bit ppg timer ppg timer : 3 channels pwm mode or single-shot mode selectable bit decoder bit decoder : 1 channel parity generator parity generator : 1 channel selectable odd/even parity ps/2 interface ps/2 interface : 3 channels 4 selectable sampling clocks lpc interface lpc bus interface : 1 channel universal peripheral interface : 4 channels ga20 output control : for upi ch 0 only data buffer array : 80 bytes serial irq controller serial irq request : 6 channels lpc clock monitor/control uart with full-duplex double buffe r (variable data length) clock asynchronized or clock synchroni zed transmission (with start and stop bits) can be selectively used i 2 c i 2 c (smbus compliant) : 1 channel support i 2 c bus of philips and the smbus proposed by intel i 2 c bus selectable packet error check timeout detection function multi-address i 2 c multi-address i 2 c (smbus compliant) : 1 channel support i 2 c bus of philips and the smbus proposed by intel i 2 c bus selectable packet error check timeout detection function 6 addresses support alert function
mb90378 series 4 (continued) * : varies with conditions such as the operating frequency (see ? electrical characteristics?). assurance for the mb90v378 is given only for operation wi th a tool at power supply voltage of 2.7 v to 3.6 v, an operating temperature of 0 c to + 25 c, and an operating frequency of 1 mhz to 20 mhz. package and corresponding products : available x : not available note : for more informati on about each package, see ? package dimensions?. differences among products memory size in evaluation with an evaluation product, note the di fference between the evaluation product and the product actually used. the following items must be taken into consideration. the mb90v378 does not have an internal rom, howeve r, operations equivalent to chips with an internal rom can be evaluated by using a dedicated development tool , enabling selection of rom size by settings of the development tool. in the mb90v378, images from ff4000 h to ffffff h are mapped to bank 00, and ff0000 h to ff3fff h are mapped to bank ff only. (this setting can be c hanged by the development tool configuration.) in the mb90f378, images from ff4000 h to ffffff h are mapped to bank 00, and ff0000 h to ff3fff h are mapped to bank ff only. part number parameter mb90f378 mb90v378 bridge circuit three bus connection routes can be switched by i 2 c/multi-address i 2 c dtp/external interrupt 8 independent channels selectable causes : rise/fall edge, fall edge, ?l? level or ?h? level extended external interrupt 8 multiplex channels 2 set selectable causes : rise/fall edge, fall edge, rise edge or ?l? level key-on wake-up interrupt 8 independent channels causes : ?l? level 8/10-bit a/d converter 8/10-bit resolution : 12 channels conversion time : less than 4.2 s (20 mhz internal clock) 8-bit d/a converter 8-bit resolution : 2 channels lcd controller/driver up to 9 seg 4 com selectable lcd output or cmos i/o port low-power consumption stop m ode/sleep mode/cpu intermitt ent operation mode/watch mode process cmos package lqfp-144 (fpt-144p-m12 : 0.4 mm pitch) pga299 operating voltage 2.7 v to 3.6 v at 20 mhz* package mb90f378 mb90v378 fpt-144p-m12 x pga299 x
mb90378 series 5 pin assignment 1 p40/psck0 2 36 pb2/eei10 p41/psda0 3 p42/psck1 4 p43/psda1 5 p44/psck2 6 p45/psda2 7 p 46/clkrun 8 p47/serirq 9 p50/ga20 10 p 51/lframe 11 p52/lreset 12 p53/lck 13 p54/lad0 14 p55/lad1 15 p56/lad2 16 p57/lad3 17 rst 18 v cc 19 v ss x0a 20 21 x1a 22 pa0/eei0 23 pa1/eei1 24 pa2/eei2 25 pa3/eei3 26 pa4/eei4 27 pa5/eei5 28 pa6/eei6 29 pa7/eei7 30 p83/int6 31 p84/int7 32 p85 33 p86 34 pb0/eei8 35 pb1/eei9 37 p b3/eei11 72 p81/sda1 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 p b4/eei12 p b5/eei13 p b6/eei14 p b7/eei15 av cc avr av ss pc0/an0 pc1/an1 pc2/an2 pc3/an3 pc4/an4 pc5/an5 pc6/an6 pc7/an7 pd0/an8 v cc v ss md2 md1 md0 pd1/an9 pd2/an10 pd3/an11 pd4/da1 pd5/da2 p d6/ppg2 p90/scl2 p91/sda2 p92/scl3 p93/sda3 p94/scl4 p95/sda4 p80/scl1 73 p82/alert 108 p77/ppg1 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 pe0/tin1/seg0 pe1/to1/seg1 pe2/tin2/seg2 pe3/to2/seg3 pe4/tin3/seg4 pe5/to3/seg5 pe6/tin4/seg6 pe7/to4/seg7 pf0/tin5/seg8 * pf1/to5/com0 * pf2/tin6/com1 * pf3/to6/com2 * pf4/com3* pf5/v1* pf6/v2* pf7/v3* v cc v ss pd7/ppg3 p60/int0 p61/int1 p62/int2 p63/int3 p64/int4 p65/int5 p66/uck1 p67/uo1 p70/ui1 p71/uck2 p72/uo2 p73/ui2 p74/uck3 p75/uo3 p76/ui3 109 p00/ksi0 144 p37/adt g 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 p01/ksi1 p02/ksi2 p03/ksi3 p04/ksi4 p05/ksi5 p06/ksi6 p07/ksi7 p10 p11 p12 p13 p14 p15 p16 p17 p20 v cc v ss x0 x1 p21 p22 p23 p24 p25 p26 p27 p30/pg0 0 p31/pg0 1 p32/pg1 0 p33/pg1 1 p34 p35 p36 lqfp-144 * : heavy current pins (fpt-144p-m12) top view
mb90378 series 6 pin description (continued) pin no. pin name i/o circuit pin status during reset function lqfp-144 128,129 x0,x1 a oscillating main oscillation i/o pins. 20,21 x0a,x1a a oscillating sub-clock oscillation i/o pins. 17 rst b reset input external reset input pin. 58, 57, 56 md0 to md2 c mode input input pin for operation mode spec ification. connect this pin directly to vcc or vss. 109 to 116 p00 to p07 d port input general-purpose i/o ports. ksi0 to ksi7 can be used as key-on wake-up interrupt input ch 0 to 7. input is enabled when 1 is set in ei cr : en0 to 7 in standby mode. 117 to 124 p10 to p17 e general-purpose i/o ports. 125, 130 to 136 p20 to p27 e general-purpose i/o ports. 137, 138 p30, p31 e general-purpose i/o ports. pg00, pg01 8/16-bit ppg timer output pins. 8-bit x 2 channels mode use : event output from pg00/pg01 16-bit x 1channel mode use : event output from pg00 139, 140 p32, p33 e general-purpose i/o ports. pg10, pg11 8/16-bit ppg timer output pins. 8-bit x 2 channels mode use : event output from pg10/pg11. 16-bit x 1channel mode use : event output from pg10. 141 to 143 p34 to p36 e general-purpose i/o ports. 144 p37 e general-purpose i/o port. adtg external trigger input pin (adtg) for the a/d converter. 1 p40 f general-purpose nch open-drain i/o port. psck0 serial clock i/o pin for ps/2 in terface ch 0. this function is selected when ps/2 interface ch 0 is enabled. 2 p41 f general-purpose nch open-drain i/o port. psda0 serial data i/o pin for ps/2 inte rface ch 0. this function is selected when ps/2 interface ch 0 is enabled. 3 p42 f general-purpose nch open-drain i/o port. psck1 serial clock i/o pin for ps/2 inte rface ch 1. this function is selected when ps/2 interface ch 1 is enabled. 4 p43 f general-purpose nch open-drain i/o port. psda1 serial data i/o pin for ps/2 inte rface ch 1. this function is selected when ps/2 interface ch 1 is enabled.
mb90378 series 7 (continued) pin no. pin name i/o circuit pin status during reset function lqfp-144 5 p44 f port input general-purpose nch open-drain i/o port. psck2 serial clock i/o pin for ps/2 inte rface ch 2. this function is selected when ps/2 interface ch 2 is enabled. 6 p45 f general-purpose nch open-drain i/o port. psda2 serial data i/o pin for ps/2 inte rface ch 2. this function is selected when ps/2 interface ch 2 is enabled. 7 p46 g general-purpose nch open-drain i/o port. clkrun lpc clock status / restart request i/o pin for serial irq controller. this function is selected when serial irq and lpc clock restart request is enabled. 8 p47 h general-purpose i/o port. serirq serial irq data i/o pin for serial irq controller. this function is selected when serial irq is enabled. 9 p50 j general-purpose nch open-drain i/o port. ga20 ga20 output for lpc interface. this function is selected when ga20 function is enabled. 10 p51 h general-purpose i/o port. lframe lframe input for lpc interface. this function is selected when lpc interface is enabled. 11 p52 h general-purpose i/o port. lreset reset input for lpc interface. this function is selected when lpc interface is enabled. 12 p53 h general-purpose i/o port. lck clock input for lpc interface. this function is selected when lpc interface is enabled. 13 to 16 p54 to p57 h general-purpose i/o ports. lad0 to lad3 address/data i/o for lpc interfac e. this function is selected when lpc interface is enabled. 93 to 98 p60 to p65 i general-purpose i/o ports. int0 to int5 can be used as dtp/external inte rrupt request input ch 0 to 5. input is enabled when 1 is set in enir: en0 to 5 in standby mode. 99 p66 i general-purpose i/o port. uck1 serial clock i/o pin for uart ch 1. this function is enabled when uart ch 1 enables clock output.
mb90378 series 8 (continued) pin no. pin name i/o circuit pin status during reset function lqfp-144 100 p67 i port input general-purpose i/o port. uo1 serial data output pin for uart ch 1. this function is enabled when uart ch 1 enables data output. 101 p70 i general-purpose i/o port. ui1 serial data input pin for uart ch 1. while uart ch 1 is operating for input, the input of this pin is used as required and must not be used for any other input. 102 p71 i general-purpose i/o port. uck2 serial clock i/o pin for uart ch 2. this function is enabled when uart ch 2 enables clock output. 103 p72 i general-purpose i/o port. uo2 serial data output pin for uart ch 2. this function is enabled when uart ch 2 enables data output. 104 p73 i general-purpose i/o port. ui2 serial data input pin for uart ch 2. while uart ch 2 is operating for input, the input of this pin is used as required and must not be used for any other input. 105 p74 i general-purpose i/o port. uck3 serial clock i/o pin for uart ch 3. this function is enabled when uart ch 3 enables clock output. 106 p75 i general-purpose i/o port. uo3 serial data output pin for uart ch 3. this function is enabled when uart ch 3 enables data output. 107 p76 i general-purpose i/o port. ui3 serial data input pin for uart ch 3. while uart ch 3 is operating for input, the input of this pin is used as required and must not be used for any other input. 108 p77 i general-purpose i/o port. ppg1 output pin for ppg ch 1. this function is enabled when ppg ch 1 output is enabled. 71 p80 t general-purpose nch open-drain i/o port. scl1 serial clock i/o pin for multi-address i 2 c. 72 p81 t general-purpose nch open-drain i/o port. sda1 serial data i/o pin for multi-address i 2 c.
mb90378 series 9 (continued) pin no. pin name i/o circuit pin status during reset function lqfp-144 73 p82 j port input general-purpose nch open-drain i/o port. alert alert output pin for multi-address i 2 c. 30, 31 p83, p84 i general-purpose i/o ports. int6, int7 can be used as dtp/external in terrupt request input ch6, 7. input is enabled when 1 is set in enir: en6, 7 in standby mode. 32 p85 i general-purpose i/o port. 33 p86 i general-purpose i/o port. 65 p90 t general-purpose nch open-drain i/o port. scl2 serial clock i/o pin for bridge circuit. 66 p91 t general-purpose nch open-drain i/o port. sda2 serial data i/o pin for bridge circuit. 67 p92 t general-purpose nch open-drain i/o port. scl3 serial clock i/o pin for bridge circuit. 68 p93 t general-purpose nch open-drain i/o port. sda3 serial data i/o pin for bridge circuit. 69 p94 t general-purpose nch open-drain i/o port. scl4 serial clock i/o pin for bridge circuit. 70 p95 t general-purpose nch open-drain i/o port. sda4 serial data i/o pin for bridge circuit. 22 to 29 pa0 to pa7 i general-purpose i/o ports. eei0 to eei7 external irq input pin for extend external interrupt request ch0 to 7. when irq detect, prepare to th e cpu interrupt. (multiplex) 34 to 41 pb0 to pb7 i general-purpose i/o ports. eei8 to eei15 external irq input pin for extend external interrupt request ch8 to 15. when irq detect, prepare to th e cpu interrupt. (multiplex) 45 to 52 pc0 to pc7 m a/d input general-purpose i/o ports. an0 to an7 a/d converter analog input pin 0 to 7. this function is enabled when the analog input specific ation is enabled (ader1). 53, 59 to 61 pd0 to pd3 m general-purpose i/o ports. an8 to an11 a/d converter analog input pin 8 to 11. this function is enabled when the analog input specific ation is enabled (ader2).
mb90378 series 10 (continued) pin no. pin name i/o circuit pin status during reset function lqfp-144 62, 63 pd4, pd5 n port input general-purpose i/o ports. da1, da2 d/a converter analog output 1, 2. this function is selected when d/a converted is enabled. 64, 92 pd6, pd7 h general-purpose i/o ports. ppg2, ppg3 output pin for ppg ch 2, 3. th is function is selected when ppg ch 2, 3 output is enabled. 74 pe0 o general-purpose i/o port. seg0 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. tin1 external clock input pin for reload timer 1. 75 pe1 o general-purpose i/o port. seg1 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. to1 event output pin for reload timer 1. 76 pe2 o general-purpose i/o port. seg2 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. tin2 external clock input pin for reload timer 2. 77 pe3 o general-purpose i/o port. seg3 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. to2 event output pin for reload timer 2. 78 pe4 o general-purpose i/o port. seg4 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. tin3 external clock input pin for reload timer 3. 79 pe5 o general-purpose i/o port. seg5 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. to3 event output pin for reload timer 3. 80 pe6 o general-purpose i/o port. seg6 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. tin4 external clock input pin for reload timer 4.
mb90378 series 11 (continued) pin no. pin name i/o circuit pin status during reset function lqfp-144 81 pe7 o port input general-purpose i/o port. seg7 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. to4 event output pin for reload timer 4. 82 pf0 p general-purpose nch open-drain i/o port. seg8 segment output pin for lcd controller/driver. this function is selected when lcd segment output is enabled. tin5 external clock input pin for reload timer 5. 83 pf1 p general-purpose nch open-drain i/o port. com0 com output pin for lcd controller/driver. this function is select- ed when lcd com output is enabled. to5 event output pin for reload timer 5. 84 pf2 p general-purpose nch open-drain i/o port. com1 com output pin for lcd controller/driver. this function is select- ed when lcd com output is enabled. tin6 external clock input pin for reload timer 6. 85 pf3 p general-purpose nch open-drain i/o port. com2 com output pin for lcd controller/driver. this function is select- ed when lcd com output is enabled. to6 event output pin for reload timer 6. 86 pf4 p general-purpose nch open-drain i/o port. com3 com output pin for lcd controller/driver. this function is select- ed when lcd com output is enabled. 87 to 89 pf5 to pf7 q power input general-purpose nch open-drain i/o ports. v1 to v3 power input pin for lcd controller/driver. this function is select- ed when external voltage divider is enabled. 42 av cc r power input vcc power input pin for analog circuits. 43 avr s vref+ input pin for the a/d conver ter. this voltage must not exceed vcc. vref- is fixed to av ss . 44 av ss r vss power input pin for analog circuits. 19,55,91, 127 v ss ? source power input power (0 v) input pin. 18,54,90, 126 v cc ? power (3.3 v) input pin.
mb90378 series 12 i/o circuit type (continued) type circuit remarks a main/sub clock (main/sub clock crystal oscillator) at an oscillation feedback resistor of approximately 1 m ? b cmos hysteresis input pull-up resistor approximately 50 k ? c cmos hysteresis input d cmos output cmos hysteresis input selectable pull-up resistor approximately 50 k ? i ol = 4 ma e cmos output cmos input selectable pull-up resistor approximately 50 k ? i ol = 4 ma f nch open-drain output cmos hysteresis input i ol = 4 ma 5 v tolerant xout standby mode control x1/x1a x0/x0a nch pch nch pch r cmos hysteresis input cmos hysteresis inp ut r pch pch nch pout nout pull-up control cmos hysteresis input standby mode control r pch pch nch pout nout pull-up control cmos input standby mode control nch nch nout cmos hysteresis input standby mode control
mb90378 series 13 (continued) type circuit remarks g nch open-drain output cmos input i ol = 4 ma h cmos output cmos input i ol = 4 ma i cmos output cmos hysteresis input i ol = 4 ma j nch open-drain output cmos input i ol = 4 ma 5 v tolerant m cmos output cmos input a/d analog input i ol = 4 ma pch nch nout cmos input standby mode control pch nch nout cmos input standby mode control pout pch nch nout cmos hysteresis input standby mode control pout cmos input standby mode control nout nch nch pch nch nout cmos input standby mode control pout analog input
mb90378 series 14 (continued) type circuit remarks n cmos output cmos input d/a analog output i ol = 4 ma o cmos output cmos hysteresis input segment output i ol = 4 ma p nch open-drain output cmos hysteresis input segment output i ol = 12 ma q nch open-drain output cmos hysteresis input lcd driving power supply i ol = 12 ma pch nch nout cmos input standby mode control pout analog input pch nch nout cmos hysteresis input standby mode control pout segment output r nch nch nout cmos hysteresis input standby mode control segment output r nch nch nout cmos hysteresis input standby mode control lcd driving power supply
mb90378 series 15 (continued) type circuit remarks r power supply input protection circuit s a/d converter reference voltage (avr) input pin with protection circuit t nch open-drain output cmos input i ol = 4 ma 5 v tolerant in pch nch in pch nch analog input enable analog input enable cmos input standby mode control nout nch nch
mb90378 series 16 handling devices 1. be sure that the maximum rated voltage is not exceeded (latch-up prevention). a latch-up may occur on a cmos ic if a voltage higher than v cc or lower than v ss is applied to an input or output pin other than medium-to-high voltage pins. a latch-up may also occur if a voltage higher than the rating is applied between v cc pin and v ss pin. a latch-up causes a rapid increase in the power supply current, which can result in thermal damage to an element. take utmost care that the maximum rated voltage is not exceeded. when turning the power on or off to analog circuits, be sure that the analog supply voltages (av cc , avr) and analog input voltage do not exceed the digital supply voltage (v cc ). 2. stabilize the supply voltages even within the operation guarantee range of the v cc supply voltage, a malfunction can be caused if the supply voltage undergoes a rapid change. for voltage stabilization guidelines, the v cc ripple fluctuations (p-p value) at commercial frequencies (50 hz to 60 hz) should be suppressed to "10%" or less of the reference v cc value. during a momentary change such as when switching a s upply voltage, voltage fluctuations should also be suppressed so that the "transient fluc tuation rate" is 0.1 v/ms or less. 3. power-on to prevent a malfunction in the built -in voltage drop circuit, secure "50 s (between 0.2 v and 1.8 v)" or more for the voltage rise time during power-on. 4. treatment of unused input pins an unused input pin may cause a malfunction if it is left open. every unused input pin should be pulled up or down. 5. treatment of a/d converter, and d/a converter power pin when the a/d converter, d/a converter and comparator is not used, connect the pins as follows: av cc = v cc , av ss = avr = v ss . 6. notes on external clock when an external clock is used, the oscillation stabilizatio n wait time is required at power-on reset or at cancel- lation of sub-clock mode or stop mode. as shown in diagram below, when an external clock is used, connect only the x0 pin and leave the x1 pin open. open x1 x0 mb90378 series
mb90378 series 17 7. power supply pins when a device has two or more v cc or v ss pins, the pins that should have equal potential are connected within the device in order to prevent a latch-up or other ma lfunction. to reduce extra neous emission, to prevent a malfunction of the strobe signal due to an increase in the group level, and to main tain the local output current rating, connect all these power supply pins to an external power supply and ground them. the current source should be connected to the v cc and v ss pins of the device with minimum impedance. it is recommended that a bypass capacitor of about 0.1 f be connected near the terminals between v cc and v ss . 8. analog power-on sequence of a/d converter and d/a converter the power to the a/d converter and d/a converter (av cc , avr) and analog inputs (an0 to an11) must be turned on after the power to the digital circuits (v cc ) is turned on. when turning off the power, turn off the power to the digital circuits (v cc ) after turning off the power to the a/d converter, d/a converter and analog inputs. when the power is turned on or off, avr should not exceed av cc . also, when a pin that is used for a/d analog input is also used as an input port, the inpu t voltage should not exceed av cc . (the power to the analog circuits and the power to the digital circuits can be simultaneously turned on or off.)
mb90378 series 18 block diagram other pins clock control circuit x0, x0a x1, x1a rst 8 8 8 8 p00/ksi0 to p07/ksi7 p10 to p17 p20 to p27 p30/pg00 to p33/pg11 p34 to p36 p37/adtg p40/psck0 p41/psda0 p42/psck1 p43/psda1 p44/psck2 p45/psda2 p47/serirq p46/clkrun p50/ga20 p51/lframe p52/lreset p53/lck p54/lad0 p55/lad1 p56/lad2 p57/lad3 6 p60/int0 to p65/int5 p66/uck1 p67/uo1 p70/ui1 p71/uck2 p72/uo2 p73/ui2 p74/uck3 p75/uo3 p76/ui3 p77/ppg1 8 6 6 2 7 6 3 3 6 6 8 8 8 8 2 12 2 2 6 6 16 p80/scl1 p81/sda1 p82/alert p90/scl2 p91/sda2 p92/scl3 p93/sda3 p94/scl4 p95/sda4 pa0/eei0 to pa7/eei7 pb0/eei8 to pb7/eei15 p83/int6 p84/int7 p85 p86 pc0/an0 to pc7/an7 pd0/an8 to pd3/an11 pd4/da1 pd5/da2 pd6/ppg2 pd7/ppg3 pe0/tin1/seg0 pe1/to1/seg1 pe2/tin2/seg2 pe3/to2/seg3 pe4/tin3/seg4 pe5/to3/seg5 pe6/tin4/seg6 pe7/to4/seg7 pf0/seg8/tin5* pf1/com0/to5* pf2/com1/tin6* pf3/com2/to6* pf4/com3* pf5/v1* to pf7/v3* f 2 mc-16lx bus reset circuit (watchdog timer) interrupt controller timebase timer cmos i/o port 0, 1, 2, 3* key-on wake-up interrupt 8/16-bit ppg timer (ch1, ch2) nch open-drain i/o port 4 (p47 is cmos i/o port) serial irq (6 channels) lpc interface ga20 control upi (ch0, ch1, ch2, ch3) bus interface nch open-drain i/o p50 cmos i/o p51 to p57 dtp/external interrupt ch0, 1, 2, 3, 4, 5 uart (ch1, ch2, ch3) 16-bit ppg (ch1) cmos i/o port 6, 7 ram 6kb flash 128 kb mirroring flash security cpu f 2 mc-16lx family core v ss x 4, v cc x4, md0 to md2, av cc , av ss , avr 3ch ps/2 interface delayed interrupt generator nch open-drain i/o port 8, 9 i 2 c bus (multi-address) i 2 c bus bridge circuit cmos i/o port a, b, 8 extend external interrupt 1 (8 channels) extend external interrupt 2 (8 channels) dtp/external interrupt (ch6, ch7) 8/10-bit a/d converter (12 channels) 8-bit d/a converter (2 channels) 16-bit ppg (ch2, ch3) cmos i/o port c, d cmos i/o port e nch open-drain i/o port f 16-bit reload timer (ch1, ch2, ch3, ch4, ch5, ch6) lcd controller/driver (9seg x 4com) * : p00 to p07, p10 to p17, p20 to p 27, p30 to p37 : with resistors that can be used as input pull-up resistors. pf0 to pf7 : high current pins
mb90378 series 19 memory map * : the mb90v378 does not contain rom. assume that the development tool uses these area for its rom decode areas. notes : ? if single-chip mode (without rom mirroring function ) is selected, see chapter 32, "rom mirroring function selection module" of the mb90378 series h/w manual. ? rom data in the ff bank can be seen as an image in the higher 00 bank to validate the small model c compiler. because addresses of the 16 low-order bi ts in the ff bank are the same, the table in rom can be referenced without the "far" spec ification. for example, when 00c000 h is accessed, the contents of rom at ffc000 h are actually accessed. the rom area in the ff bank exceed s 48 kbytes, and all areas cannot be seen as images in the 00 bank. because rom data from ff4000 h to ffffff h is seen as an image at 004000 h to 00ffff h , the rom data table should be stored in the area from ff4000 h to ffffff h . model address #1 address #2 address #3 mb90f378 fe0000 h 004000 h 001900 h mb90v378 fe0000 h * 004000 h * 003f80 h rom area rom area (ff bank image) peripheral area ram area register peripheral area single-chip mode (with rom mirroring function) ffffff h a ddress #1 fc0000 h 010000 h a ddress #2 004000 h 003f80 h a ddress #3 000100 h 0000f8 h 000000 h : internal access memo ry : access not allowed
mb90378 series 20 f 2 mc-16lx cpu programming model dedicated registers general-purpose registers ah al usp ssp ps pc dpr pcb dtb usb ssb adb 8-bit 16-bit 32-bit accumulator (a) user stack pointer (usp) system stack pointer (ssp) processor status (ps) program counter (pc) direct page register (dpr) program bank register(pcb) data bank register (dtb) user stack bank register (usb) system stack bank register (ssb) additional data bank register (adb ) cpu dedicated register accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register internal bus ram ram general-purpose register
mb90378 series 21 processor status (ps) ps default value default value default value default value 15 13 12 8 7 0 000 ilm rp 00000 ccr -01xxxxx 76 543 210 -istnzvc -01xxxxx b4 b3 b2 b1 b0 000 00 000 ilm2 ilm1 ilm0 : ccr : rp : ilm - : not used x : undefined
mb90378 series 22 i/o map (continued) address abbreviation register byte access word access resource name initial value 000000 h pdr0 port 0 data register r/w r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w r/w port 4 x1111111 b 000005 h pdr5 port 5 data register r/w r/w port 5 xxxxxxx1 b 000006 h pdr6 port 6 data register r/w r/w port 6 xxxxxxxx b 000007 h pdr7 port 7 data register r/w r/w port 7 xxxxxxxx b 000008 h pdr8 port 8 data register r/w r/w port 8 -xxxx111 b 000009 h pdr9 port 9 data register r/w r/w port 9 --111111 b 00000a h pdra port a data register r/w r/w port a xxxxxxxx b 00000b h pdrb port b data register r/w r/w port b xxxxxxxx b 00000c h pdrc port c data register r/w r/w port c xxxxxxxx b 00000d h pdrd port d data register r/w r/w port d xxxxxxxx b 00000e h pdre port e data register r/w r/w port e xxxxxxxx b 00000f h pdrf port f data register r/w r/w port f 11111111 b 000010 h ddr0 port 0 direction register r/w r/w port 0 00000000 b 000011 h ddr1 port 1 direction register r/w r/w port 1 00000000 b 000012 h ddr2 port 2 direction register r/w r/w port 2 00000000 b 000013 h ddr3 port 3 direction register r/w r/w port 3 00000000 b 000014 h ddr4 port 4 direction register r/w r/w port 4 0------- b 000015 h ddr5 port 5 direction register r/w r/w port 5 0000000- b 000016 h ddr6 port 6 direction register r/w r/w port 6 00000000 b 000017 h ddr7 port 7 direction register r/w r/w port 7 00000000 b 000018 h pgdr parity generator data register r/w r/w parity generator xxxxxxxx b 000019 h pgcsr parity generator control status register r/w r/w x------0 b 00001a h ddra port a direction register r/w r/w port a 00000000 b 00001b h ddrb port b direction register r/w r/w port b 00000000 b 00001c h ddrc port c direction register r/w r/w port c 00000000 b 00001d h ddrd port d direction register r/w r/w port d 00000000 b 00001e h ddre port e direction register r/w r/w port e 00000000 b 00001f h ddr8 port 8 direction register r/w r/w port 8 -0000--- b
mb90378 series 23 (continued) address abbreviation register byte access word access resource name initial value 000020 h smr1 serial mode register 1 r/w r/w uart1 00000-00 b 000021 h scr1 serial control register 1 r/w r/w 00000100 b 000022 h sidr1/ sodr1 input data register 1/ output data register 1 r/w r/w xxxxxxxx b 000023 h ssr1 serial status register 1 r/w r/w 00001000 b 000024 h m2cr1 mode 2 control register 1 r/w r/w ----1000 b 000025 h cdcr1 clock division control register 1 r/w r/w communication prescaler 1 00--0000 b 000026 h enir interrupt/dtp enable register r/w r/w dtp/external interrupt 00000000 b 000027 h eirr interrupt/dtp cause register r/w r/w xxxxxxxx b 000028 h elvr request level setting register r/w r/w 00000000 b 000029 h r/w r/w 00000000 b 00002a h ader1 analog input enable register 1 r/w r/w port c, a/d 11111111 b 00002b h ader2 analog input enable register 2 r/w r/w port d, a/d ----1111 b 00002c h brsr bridge circuit selection regi ster r/w r/w bridge circuit --000000 b 00002d h adc0 a/d control register r/w r/w 8/10-bit a/d converter 00000000 b 00002e h adcr0 a/d data register r r xxxxxxxx b 00002f h adcr1 r/w r/w 00000-xx b 000030 h adcs0 a/d control status register r/w r/w 00-------- b 000031 h adcs1 r/w r/w 00000000 b 000032 h sicrl serial interrupt request register r/w r/w serial irq 00000000 b 000033 h sicrh serial interrupt control register r/w r/w 00000000 b 000034 h sifr1 serial interrupt frame number register 1 r/w r/w --000000 b 000035 h sifr2 serial interrupt frame number register 2 r/w r/w --000000 b 000036 h sifr3 serial interrupt frame number register 3 r/w r/w --000000 b 000037 h sifr4 serial interrupt frame number register 4 r/w r/w --000000 b 000038 h pdcrl1 ppg1 down counter register ? r 16-bit ppg timer (ch1) 11111111 b 000039 h pdcrh1 ? r 11111111 b 00003a h pcsrl1 ppg1 period setting register ? w xxxxxxxx b 00003b h pcsrh1 ? w xxxxxxxx b 00003c h pdutl1 ppg1 duty setting register ? w xxxxxxxx b 00003d h pduth1 ? w xxxxxxxx b 00003e h pcntl1 ppg1 control status register r/w r/w --000000 b 00003f h pcnth1 r/w r/w 00000000 b
mb90378 series 24 (continued) address abbreviation register byte access word access resource name initial value 000040 h pdcrl2 ppg2 down counter register ? r 16-bit ppg timer (ch2) 11111111 b 000041 h pdcrh2 ? r 11111111 b 000042 h pcsrl2 ppg2 period setting register ? w xxxxxxxx b 000043 h pcsrh2 ? w xxxxxxxx b 000044 h pdutl2 ppg2 duty setting register ? w xxxxxxxx b 000045 h pduth2 ? w xxxxxxxx b 000046 h pcntl2 ppg2 control status register r/w r/w --000000 b 000047 h pcnth2 r/w r/w 00000000 b 000048 h pdcrl3 ppg3 down counter register ? r 16-bit ppg timer (ch3) 11111111 b 000049 h pdcrh3 ? r 11111111 b 00004a h pcsrl3 ppg3 period setting register ? w xxxxxxxx b 00004b h pcsrh3 ? w xxxxxxxx b 00004c h pdutl3 ppg3 duty setting register ? w xxxxxxxx b 00004d h pduth3 ? w xxxxxxxx b 00004e h pcntl3 ppg3 control status register r/w r/w --000000 b 00004f h pcnth3 r/w r/w 00000000 b 000050 h pscr0 ps/2 interface control register 0 r/w r/w 3-channel ps/2 interface 0--00000 b 000051 h pssr0 ps/2 interface status register 0 r/w r/w 00000000 b 000052 h pscr1 ps/2 interface contro l register 1 r/w r/w 0--00000 b 000053 h pssr1 ps/2 interface status register 1 r/w r/w 00000000 b 000054 h pscr2 ps/2 interface contro l register 2 r/w r/w 0--00000 b 000055 h pssr2 ps/2 interface status register 2 r/w r/w 00000000 b 000056 h psdr0 ps/2 interface data register 0 r/w r/w 00000000 b 000057 h psdr1 ps/2 interface data register 1 r/w r/w 00000000 b 000058 h psdr2 ps/2 interface data register 2 r/w r/w 00000000 b 000059 h psmr ps/2 interface mode register r/w r/w ----0000 b 00005a h dat0 d/a converter data register 0 r/w r/w 8-bit d/a converter xxxxxxxx b 00005b h dat1 d/a converter data register 1 r/w r/w xxxxxxxx b 00005c h dacr0 d/a control register 0 r/w r/w -------0 b 00005d h dacr1 d/a control register 1 r/w r/w -------0 b
mb90378 series 25 (continued) address abbreviation register byte access word access resource name initial value 00005e h upal1 upi1 address register (lower) r/w r/w lpc interface xxxxxxxx b 00005f h upah1 upi1 address register (upper) r/w r/w xxxxxxxx b 000060 h upal2 upi2 address register (lower) r/w r/w xxxxxxxx b 000061 h upah2 upi2 address register (upper) r/w r/w xxxxxxxx b 000062 h upal3 upi3 address register (lower) r/w r/w xxxxxxxx b 000063 h upah3 upi3 address register (upper) r/w r/w xxxxxxxx b 000064 h upcl upi control register (lower) r/w r/w 00000000 b 000065 h upch upi control register (upper) r/w r/w -000-000 b 000066 h updi0/ updo0 upi0 data input register/ data output register r/w r/w xxxxxxxx b 000067 h ups0 upi0 status register r/w r/w 00000000 b 000068 h updi1/ updo1 upi1 data input register/ data output register r/w r/w xxxxxxxx b 000069 h ups1 upi1 status register r/w r/w 00000000 b 00006a h updi2/ updo2 upi2 data input register/ data output register r/w r/w xxxxxxxx b 00006b h ups2 upi2 status register r/w r/w 00000000 b 00006c h updi3/ updo3 upi3 data input register/ data output register r/w r/w xxxxxxxx b 00006d h ups3 upi3 status register r/w r/w 00000000 b 00006e h lcr lpc control register r/w r/w -----000 b 00006f h romm rom mirroring function selection register ww rom mirroring function -------1 b 000070 h tmcsrl1 timer control status register ch1 (lower) r/w r/w 16-bit reload timer (ch1) 00000000 b 000071 h tmcsrh1 timer control status register ch1 (upper) r/w r/w ----0000 b 000072 h tmr1/ tmrd1 16-bit timer/reload register ch1 ? r/w xxxxxxxx b 000073 h ? r/w xxxxxxxx b 000074 h tmcsrl2 timer control status register ch2 (lower) r/w r/w 16-bit reload timer (ch2) 00000000 b 000075 h tmcsrh2 timer control status register ch2 (upper) r/w r/w ----0000 b 000076 h tmr2/ tmrd2 16-bit timer/reload register ch2 ? r/w xxxxxxxx b 000077 h ? r/w xxxxxxxx b
mb90378 series 26 (continued) address abbreviation register byte access word access resource name initial value 000078 h tmcsrl3 timer control status register ch3 (lower) r/w r/w 16-bit reload timer (ch3) 00000000 b 000079 h tmcsrh3 timer control status register ch3 (upper) r/w r/w ----0000 b 00007a h tmr3/ tmrd3 16-bit timer/reload register ch3 ? r/w xxxxxxxx b 00007b h ? r/w xxxxxxxx b 00007c h tmcsrl4 timer control status register ch4 (lower) r/w r/w 16-bit reload timer (ch4) 00000000 b 00007d h tmcsrh4 timer control status register ch4 (upper) r/w r/w ----0000 b 00007e h tmr4/ tmrd4 16-bit timer/reload register ch4 ? r/w xxxxxxxx b 00007f h ? r/w xxxxxxxx b 000080 h ibcrl i 2 c bus control register (lower) r/w r/w i 2 c ----0000 b 000081 h ibcrh i 2 c bus control register (upper) r/w r/w 00000000 b 000082 h ibsrl i 2 c bus status register (lower) r r 00000000 b 000083 h ibsrh i 2 c bus status register (upper) r/w r/w --000000 b 000084 h idar i 2 c data register r/w r/w xxxxxxxx b 000085 h iadr i 2 c address register r/w r/w -xxxxxxx b 000086 h iccr i 2 c clock control register r/w r/w 0-000000 b 000087 h itcr i 2 c timeout control register r/w r/w -0-00000 b 000088 h itoc i 2 c timeout clock register r/w r/w 00000000 b 000089 h itod i 2 c timeout data register r/w r/w 00000000 b 00008a h isto i 2 c slave timeout register r/w r/w 00000000 b 00008b h imto i 2 c master timeout register r/w r/w 00000000 b 00008c h rdr0 port 0 pull-up resistor setting register r/w r/w port 0 00000000 b 00008d h rdr1 port 1 pull-up resistor setting register r/w r/w port 1 00000000 b 00008e h rdr2 port 2 pull-up resistor setting register r/w r/w port 2 00000000 b 00008f h rdr3 port 3 pull-up resistor setting register r/w r/w port 3 00000000 b 000090 h to 00009d h prohibited area 00009e h pacsr program address detect control status register r/w r/w address match detection 00000000 b 00009f h dirr delayed interrupt cause/ clear register r/w r/w delayed interrupt -------0 b
mb90378 series 27 (continued) address abbreviation register byte access word access resource name initial value 0000a0 h lpmcr low-power consumption mode register r/w r/w low-power consumption control register 00011000 b 0000a1 h ckscr clock selection register r/w r/w 11111100 b 0000a2 h , 0000a3 h prohibited area 0000a4 h ckmc clock modulation control register r/w r/w clock modulation -------0 b 0000a5 h to 0000a7 h prohibited area 0000a8 h wdtc watchdog control register r/w r/w watchdog timer x-xxx111 b 0000a9 h tbtc timebase timer control register r/w r/w timebase timer 1--00100 b 0000aa h wtc watch timer control register r/w r/w watch timer 10001000 b 0000ab h prohibited area 0000ac h eicr wake-up interrupt control register r/w r/w key-on wake-up interrupt 00000000 b 0000ad h eifr wake-up interrupt flag register r/w r/w -------0 b 0000ae h fmcs flash memory control status register r/w r/w flash memory interface circuit 000x0000 b 0000af h prohibited area 0000b0 h icr00 interrupt control register 00 r/w r/w interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 r/w r/w 00000111 b 0000b2 h icr02 interrupt control register 02 r/w r/w 00000111 b 0000b3 h icr03 interrupt control register 03 r/w r/w 00000111 b 0000b4 h icr04 interrupt control register 04 r/w r/w 00000111 b 0000b5 h icr05 interrupt control register 05 r/w r/w 00000111 b 0000b6 h icr06 interrupt control register 06 r/w r/w 00000111 b 0000b7 h icr07 interrupt control register 07 r/w r/w 00000111 b 0000b8 h icr08 interrupt control register 08 r/w r/w 00000111 b 0000b9 h icr09 interrupt control register 09 r/w r/w 00000111 b 0000ba h icr10 interrupt control register 10 r/w r/w 00000111 b 0000bb h icr11 interrupt control register 11 r/w r/w 00000111 b 0000bc h icr12 interrupt control register 12 r/w r/w 00000111 b 0000bd h icr13 interrupt control register 13 r/w r/w 00000111 b 0000be h icr14 interrupt control register 14 r/w r/w 00000111 b 0000bf h icr15 interrupt control register 15 r/w r/w 00000111 b
mb90378 series 28 (continued) address abbreviation register byte access word access resource name initial value 0000c0 h mbcrl mi 2 c bus control register (lower) r/w r/w multi-address i 2 c ----0000 b 0000c1 h mbcrh mi 2 c bus control register (upper) r/w r/w 00000000 b 0000c2 h mbsrl mi 2 c bus status register (lower) r r 00000000 b 0000c3 h mbsrh mi 2 c bus status register (upper) r/w r/w --000000 b 0000c4 h mdar mi 2 c data register r/w r/w xxxxxxxx b 0000c5 h malr mi 2 c alert register r/w r/w ----0000 b 0000c6 h madr1 mi 2 c address register 1 r/w r/w -xxxxxxx b 0000c7 h madr2 mi 2 c address register 2 r/w r/w -xxxxxxx b 0000c8 h madr3 mi 2 c address register 3 r/w r/w -xxxxxxx b 0000c9 h madr4 mi 2 c address register 4 r/w r/w -xxxxxxx b 0000ca h madr5 mi 2 c address register 5 r/w r/w -xxxxxxx b 0000cb h madr6 mi 2 c address register 6 r/w r/w -xxxxxxx b 0000cc h mccr mi 2 c clock control register r/w r/w 0-000000 b 0000cd h mtcr mi 2 c timeout control register r/w r/w -0-00000 b 0000ce h mtoc mi 2 c timeout clock register r/w r/w 00000000 b 0000cf h mtod mi 2 c timeout data register r/w r/w 00000000 b 0000d0 h msto mi 2 c slave timeout register r/w r/w 00000000 b 0000d1 h mmto mi 2 c master timeout register r/w r/w 00000000 b 0000d2 h smr2 serial mode register 2 r/w r/w uart2 00000-00 b 0000d3 h scr2 serial control register 2 r/w r/w 00000100 b 0000d4 h sidr2/ sodr2 input data register 2/ output data register 2 r/w r/w xxxxxxxx b 0000d5 h ssr2 status register 2 r/w r/w 00001000 b 0000d6 h m2cr2 mode 2 control register 2 r/w r/w ----1000 b 0000d7 h cdcr2 clock division control register 2 r/w r/w communication prescaler 2 00--0000 b 0000d8 h eenr1 interrupt enable register r/w r/w extend external interrupt 1 00000000 b 0000d9 h eerr1 interrupt cause register r/w r/w xxxxxxxx b 0000da h eelr1 request level setting register r/w r/w 00000000 b 0000db h r/w r/w 00000000 b 0000dc h eenr2 interrupt enable register r/w r/w extend external interrupt 2 00000000 b 0000dd h eerr2 interrupt cause register r/w r/w xxxxxxxx b 0000de h eelr2 request level setting register r/w r/w 00000000 b 0000df h r/w r/w 00000000 b 0000e0 h pdl3 port 3 data latch regist er r/w r/w port 3 data latch 00000000 b
mb90378 series 29 (continued) address abbreviation register byte access word access resource name initial value 0000e1 h bdr bit data register r/w r/w bit decoder ----xxxx b 0000e2 h brrl bit result register (lower) r r xxxxxxxx b 0000e3 h brrh bit result register (upper) r r xxxxxxxx b 0000e4 h smr3 serial mode register 3 r/w r/w uart3 00000-00 b 0000e5 h scr3 serial control register 3 r/w r/w 00000100 b 0000e6 h sidr3 / sodr3 input data register 3/ output data register 3 r/w r/w xxxxxxxx b 0000e7 h ssr3 status register 3 r/w r/w 00001000 b 0000e8 h m2cr3 mode 2 control register 3 r/w r/w ----1000 b 0000e9 h cdcr3 clock division control register 3 r/w r/w communication prescaler 3 00--0000 b 0000ea h tmcsrl5 timer control status register ch5 (lower) r/w r/w 16-bit reload timer (ch5) 00000000 b 0000eb h tmcsrh5 timer control status register ch5 (upper) r/w r/w ----0000 b 0000ec h tmr5/ tmrd5 16-bit timer/reload register ch5 ? r/w xxxxxxxx b 0000ed h ? r/w xxxxxxxx b 0000ee h lcrl lcd control register 0 r/w r/w lcd controller/driver 00010000 b 0000ef h lcrh lcd control register 1 r/w r/w 00000000 b 0000f0 h to 0000f4 h vram lcd display ram r/w - xxxxxxxx b 0000f5 h to 0000f7 h prohibited area 0000f8 h to 0000ff h external area 000100 h to 0018ff h prohibited area (ram area) 001ff0 h padr0 program address detection register 0 r/w r/w address match detection xxxxxxxx b 001ff1 h program address detection register 1 r/w r/w xxxxxxxx b 001ff2 h program address detection register 2 r/w r/w xxxxxxxx b
mb90378 series 30 (continued) address abbreviation register byte access word access resource name initial value 001ff3 h padr1 program address detection register 3 r/w r/w address match detection xxxxxxxx b 001ff4 h program address detection register 4 r/w r/w xxxxxxxx b 001ff5 h program address detection register 5 r/w r/w xxxxxxxx b 001ff6 h to 003f7f h prohibited area 003f80 h udrl10 up data register 10 (lower) r/w r/w lpc data buffer array-extend xxxxxxxx b 003f81 h udrh10 up data register 10 (upper) r/w r/w xxxxxxxx b 003f82 h udrl11 up data register 11 (lower) r/w r/w xxxxxxxx b 003f83 h udrh11 up data register 11 (upper) r/w r/w xxxxxxxx b 003f84 h udrl12 up data register 12 (lower) r/w r/w xxxxxxxx b 003f85 h udrh12 up data register 12 (upper) r/w r/w xxxxxxxx b 003f86 h udrl13 up data register 13 (lower) r/w r/w xxxxxxxx b 003f87 h udrh13 up data register 13 (upper) r/w r/w xxxxxxxx b 003f88 h udrl14 up data register 14 (lower) r/w r/w xxxxxxxx b 003f89 h udrh14 up data register 14 (upper) r/w r/w xxxxxxxx b 003f8a h udrl15 up data register 15 (lower) r/w r/w xxxxxxxx b 003f8b h udrh15 up data register 15 (upper) r/w r/w xxxxxxxx b 003f8c h udrl16 up data register 16 (lower) r/w r/w xxxxxxxx b 003f8d h udrh16 up data register 16 (upper) r/w r/w xxxxxxxx b 003f8e h udrl17 up data register 17 (lower) r/w r/w xxxxxxxx b 003f8f h udrh17 up data register 17 (upper) r/w r/w xxxxxxxx b 003f90 h udrl18 up data register 18 (lower) r/w r/w xxxxxxxx b 003f91 h udrh18 up data register 18 (upper) r/w r/w xxxxxxxx b 003f92 h udrl19 up data register 19 (lower) r/w r/w xxxxxxxx b 003f93 h udrh19 up data register 19 (upper) r/w r/w xxxxxxxx b 003f94 h udrl1a up data register 1a (lower) r/w r/w xxxxxxxx b 003f95 h udrh1a up data register 1a (upper) r/w r/w xxxxxxxx b 003f96 h udrl1b up data register 1b (lower) r/w r/w xxxxxxxx b 003f97 h udrh1b up data register 1b (upper) r/w r/w xxxxxxxx b 003f98 h udrl1c up data register 1c (lower) r/w r/w xxxxxxxx b 003f99 h udrh1c up data register 1c (upper) r/w r/w xxxxxxxx b 003f9a h udrl1d up data register 1d (lower) r/w r/w xxxxxxxx b 003f9b h udrh1d up data register 1d (upper) r/w r/w xxxxxxxx b
mb90378 series 31 (continued) address abbreviation register byte access word access resource name initial value 003f9c h udrl1e up data register 1e (lower) r/w r/w lpc data buffer array-extend xxxxxxxx b 003f9d h udrh1e up data register 1e (upper) r/w r/w xxxxxxxx b 003f9e h udrl1f up data register 1f (lower) r/w r/w xxxxxxxx b 003f9f h udrh1f up data register 1f (upper) r/w r/w xxxxxxxx b 003fa0 h dbaclr data buffer array clear register r/w r/w lpc data buffer array -----000 b 003fa1 h prohibited area 003fa2 h fwr0 flash programming control register 0 r/w r/w dual operating flash 00000000 b 003fa3 h fwr1 flash programming control register 1 r/w r/w 00000000 b 003fa4 h ssr0 sector switching register r/w r/w 00xxxxx0 b 003fa5 h to 003fae h prohibited area 003faf h pckcr pll clock control register w w pll xxxx0000 b 003fb0 h prll2 ppg reload register (lower) r/w r/w 8/16-bit ppg timer 2 xxxxxxxx b 003fb1 h prlh2 ppg reload register (upper) r/w r/w xxxxxxxx b 003fb2 h prll3 ppg reload register (lower) r/w r/w xxxxxxxx b 003fb3 h prlh3 ppg reload register (upper) r/w r/w xxxxxxxx b 003fb4 h ppgc2 ppg control register ch2 r/w r/w 00000001 b 003fb5 h ppgc3 ppg control register ch3 r/w r/w 00000001 b 003fb6 h pcs23 ppg clock control register r/w r/w 000000xx b 003fb7 h to 003fbf h prohibited area 003fc0 h udrl0 up data register 0 (lower) r/w r/w lpc data buffer array xxxxxxxx b 003fc1 h udrh0 up data register 0 (upper) r/w r/w xxxxxxxx b 003fc2 h udrl1 up data register 1 (lower) r/w r/w xxxxxxxx b 003fc3 h udrh1 up data register 1 (upper) r/w r/w xxxxxxxx b 003fc4 h udrl2 up data register 2 (lower) r/w r/w xxxxxxxx b 003fc5 h udrh2 up data register 2 (upper) r/w r/w xxxxxxxx b 003fc6 h udrl3 up data register 3 (lower) r/w r/w xxxxxxxx b 003fc7 h udrh3 up data register 3 (upper) r/w r/w xxxxxxxx b 003fc8 h udrl4 up data register 4 (lower) r/w r/w xxxxxxxx b 003fc9 h udrh4 up data register 4 (upper) r/w r/w xxxxxxxx b
mb90378 series 32 (continued) address abbreviation register byte access word access resource name initial value 003fca h udrl5 up data register 5 (lower) r/w r/w lpc data buffer array xxxxxxxx b 003fcb h udrh5 up data register 5 (upper) r/w r/w xxxxxxxx b 003fcc h udrl6 up data register 6 (lower) r/w r/w xxxxxxxx b 003fcd h udrh6 up data register 6 (upper) r/w r/w xxxxxxxx b 003fce h udrl7 up data register 7 (lower) r/w r/w xxxxxxxx b 003fcf h udrh7 up data register 7 (upper) r/w r/w xxxxxxxx b 003fd0 h udrl8 up data register 8 (lower) r/w r/w xxxxxxxx b 003fd1 h udrh8 up data register 8 (upper) r/w r/w xxxxxxxx b 003fd2 h udrl9 up data register 9 (lower) r/w r/w xxxxxxxx b 003fd3 h udrh9 up data register 9 (upper) r/w r/w xxxxxxxx b 003fd4 h udrla up data register a (lower) r/w r/w xxxxxxxx b 003fd5 h udrha up data register a (upper) r/w r/w xxxxxxxx b 003fd6 h udrlb up data register b (lower) r/w r/w xxxxxxxx b 003fd7 h udrhb up data register b (upper) r/w r/w xxxxxxxx b 003fd8 h udrlc up data register c (lower) r/w r/w xxxxxxxx b 003fd9 h udrhc up data register c (upper) r/w r/w xxxxxxxx b 003fda h udrld up data register d (lower) r/w r/w xxxxxxxx b 003fdb h udrhd up data register d (upper) r/w r/w xxxxxxxx b 003fdc h udrle up data register e (lower) r/w r/w xxxxxxxx b 003fdd h udrhe up data register e (upper) r/w r/w xxxxxxxx b 003fde h udrlf up data register f (lower) r/w r/w xxxxxxxx b 003fdf h udrhf up data register f (upper) r/w r/w xxxxxxxx b 003fe0 h dndl0 down data register 0 (lower) r r xxxxxxxx b 003fe1 h dndh0 down data register 0 (upper) r r xxxxxxxx b 003fe2 h dndl1 down data register 1 (lower) r r xxxxxxxx b 003fe3 h dndh1 down data register 1 (upper) r r xxxxxxxx b 003fe4 h dndl2 down data register 2 (lower) r r xxxxxxxx b 003fe5 h dndh2 down data register 2 (upper) r r xxxxxxxx b 003fe6 h dndl3 down data register 3 (lower) r r xxxxxxxx b 003fe7 h dndh3 down data register 3 (upper) r r xxxxxxxx b 003fe8 h dndl4 down data register 4 (lower) r r xxxxxxxx b 003fe9 h dndh4 down data register 4 (upper) r r xxxxxxxx b 003fea h dndl5 down data register 5 (lower) r r xxxxxxxx b 003feb h dndh5 down data register 5 (upper) r r xxxxxxxx b 003fec h dndl6 down data register 6 (lower) r r xxxxxxxx b 003fed h dndh6 down data register 6 (upper) r r xxxxxxxx b
mb90378 series 33 (continued) meaning of abbreviations used for reading and writing r/w : readable and writable r : read-only w : write-only explanation of initial values 0 : the bit is initialized to 0. 1 : the bit is initialized to 1. x : the initial value of the bit is undefined. - : the bit is not used. its initial value is undefined. instruction using io addressing e.g. mov a, io, is not supported for registers area 003f80 h to 003fff h . address abbreviation register byte access word access resource name initial value 003fee h dndl7 down data register 7 (lower) r r lpc data buffer array xxxxxxxx b 003fef h dndh7 down data register 7 (upper) r r xxxxxxxx b 003ff0 h dbaal data buffer array address register (lower) r/w r/w xxxxxxxx b 003ff1 h dbaah data buffer array address register (upper) r/w r/w xxxxxxxx b 003ff2 h , 003ff3 h prohibited area 003ff4 h tmcsrl6 timer control status register ch6 (lower) r/w r/w 16-bit reload timer (ch6) 00000000 b 003ff5 h tmcsrh6 timer control status register ch6 (upper) r/w r/w ----0000 b 003ff6 h tmr6/ tmrd6 16-bit timer/reload register ch6 ? r/w xxxxxxxx b 003ff7 h ? r/w xxxxxxxx b 003ff8 h prll0 ppg reload register (lower) r/w r/w 8/16-bit ppg timer 1 xxxxxxxx b 003ff9 h prlh0 ppg reload register (upper) r/w r/w xxxxxxxx b 003ffa h prll1 ppg reload register (lower) r/w r/w xxxxxxxx b 003ffb h prlh1 ppg reload register (upper) r/w r/w xxxxxxxx b 003ffc h ppgc0 ppg control register ch0 r/w r/w 00000001 b 003ffd h ppgc1 ppg control register ch1 r/w r/w 00000001 b 003ffe h pcs01 ppg clock control register r/w r/w 000000xx b 003fff h prohibited area
mb90378 series 34 interrupt factors, interrupt vectors, interrupt control register (continued) interrupt cause ei 2 os support interrupt vector interrupt control register priority* 2 number address icr address reset #08 08 h ffffdc h ?? high low int9 instruction #09 09 h ffffd8 h ?? exception processing #10 0a h ffffd4 h ?? a/d converter conversion termination #11 0b h ffffd0 h icr00 0000b0 h * 1 timebase timer #12 0c h ffffcc h upi0 ibf/lpc reset #13 0d h ffffc8 h icr01 0000b1 h * 1 upi1 ibf #14 0e h ffffc4 h upi2 ibf #15 0f h ffffc0 h icr02 0000b2 h * 1 upi3 ibf #16 10 h ffffbc h dtp/ext. interrupt channels 0/1 detection #17 11 h ffffb8 h icr03 0000b3 h * 1 dtp/ext. interrupt channels 2/3 detection #18 12 h ffffb4 h dtp/ext. interrupt channels 4/5 detection #19 13 h ffffb0 h icr04 0000b4 h * 1 key-on wake-up interrupt detection #20 14 h ffffac h upi0/1/2/3 obe #21 15 h ffffa8 h icr05 0000b5 h * 2 16-bit ppg timer 1 / 8/16-bit ppg timer 0/1 #22 16 h ffffa4 h ps/2 interface 0/1 #23 17 h ffffa0 h icr06 0000b6 h * 1 ps/2 interface 2 #24 18 h ffff9c h watch timer #25 19 h ffff98 h icr07 0000b7 h * 1 i 2 c transfer complete / bus error #26 1a h ffff94 h 16-bit ppg timer 2/3 #27 1b h ffff90 h icr08 0000b8 h * 1 dtp/ext. interrupt channels 6/7 detection #28 1c h ffff8c h multi-address i 2 c transfer complete / bus error #29 1d h ffff88 h icr09 0000b9 h * 1 extend external interrupt 00 to 07/08 to 15 #30 1e h ffff84 h i 2 c timeout / standby wake-up #31 1f h ffff80 h icr10 0000ba h * 1 16-bit reload timer 1/2/5 underflow #32 20 h ffff7c h multi-address i 2 c timeout / standby wake-up #33 21 h ffff78 h icr11 0000bb h * 1 16-bit reload timer 3/4/6 underflow #34 22 h ffff74 h uart1 receive #35 23 h ffff70 h icr12 0000bc h * 1 uart1 send #36 24 h ffff6c h uart2 receive #37 25 h ffff68 h icr13 0000bd h * 1 uart2 send #38 26 h ffff64 h uart3 receive #39 27 h ffff60 h icr14 0000be h * 1 uart3 send #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h * 1 delayed interrupt generator module #42 2a h ffff54 h
mb90378 series 35 (continued) : can be used and interrupt request flag is cleared by ei 2 os interrupt clear signal. : cannot be used. : can be used and support the ei 2 os stop request. : can be used. *1 : ? for peripheral functions that share the icr register, the interrupt level will be the same. ? if the extended intelligent i/o service is to be used with a peripheral function that shares the icr register with another peripheral function, the service can be started by either of the function. and if ei 2 os clear is supported, both interrupt reque st flags for the two interrupt causes are cleared by ei 2 os interrupt clear signal. it is recommended to mask either of the interrupt request during the use of ei 2 os. ? ei 2 os service cannot be started multiple times simult aneously. interrupt other t han the operating interrupt is masked during ei 2 os operation. it is recommended to mask ei ther of the interrupt requests during the use of ei 2 os. *2 : this priority is applied when interr upts of the same level occur simultaneously.
mb90378 series 36 electrical characteristics 1. absolute maximum rating (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 4.0 v av cc v ss ? 0.3 v ss + 4.0 v v cc av cc * 2 a/d converter reference input voltage* 1 avr v ss ? 0.3 v ss + 4.0 v av cc avr, avr av ss lcd power supply voltage* 1 v1 to v3 v ss ? 0.3 v ss + 4.0 v v1 to v3 must not exceed v cc input voltage* 1 v i1 v ss ? 0.3 v ss + 4.0 v all pins except p40 to p45, p80 to p82, p90 to p95 * 3 v i2 v ss ? 0.3 v ss + 6.0 v p40 to p45, p80 to p82, p90 to p95 output voltage* 1 v o v ss ? 0.3 v ss + 4.0 v *3 maximum clamp current i clamp ? 2.0 + 2.0 ma *5 total maximum clamp current |i clamp | ? 20 ma *5 ?l? level maximum output current i ol1 ? 10 ma all pins except pf0 to pf7 * 4 i ol2 ? 20 ma pf0 to pf7 * 4 ?l? level average output current i olav1 ? 4ma all pins except pf0 to pf7 average output current = operating current operating efficiency i olav2 ? 12 ma pf0 to pf7 average output current = operating current operating efficiency ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma average output current = operating current operating efficiency ?h? level maximum output current i oh ?? 10 ma *4 ?h? level average output current i ohav ?? 3ma average output current = operating current operating efficiency ?h? level total maximum output current i oh ?? 100 ma ?h? level total average output current i ohav ?? 50 ma average output current = operating current operating efficiency power consumption p d ? 200 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c
mb90378 series 37 (continued) *1 : this parameter is based on v ss = av ss = 0.0 v. *2 : set av cc and v cc at the same voltage. take care so that avr does not exceed v cc + 0.3 v when the power is turned on. *3 : v i and v o shall never exceed v cc + 0.3 v. *4 : the maximum output current is a peak value for a corresponding pin. *5 : ? use within recommended operating conditions. ? use at dc voltage (current). ? the + b signal should always be applied a limiting resistance placed between the + b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the + b signal is applied the input current to the microcontroller pin does not exceed rated values , either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the + b input potential may pass through the protective diode and increas e the potential at the vcc pin, and this may affect other devices. ? note that if a + b signal is input when the microcontroller power supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the + b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be suff icient to poerate the power-on reset. ? care must be taken not to leave the + b input pin open. ? note that analog system input/output pins other than t he a/d input pins (lcd driv e pins, etc.) cannot accept + b signal input. ? sample recommended circuits : warning: semiconductor devices can be permanently dam aged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. pch nch v cc r ? input/output equivalent circuits protective diode limiting resistance + b input (0 v to 16 v)
mb90378 series 38 2. recommended operating conditions (v ss = av ss = 0.0 v) *1 : the operating voltage varies with the operation frequency. *2 : set av cc and v cc at the same voltage. *3 : take care so that avr does not exceed v cc + 0.3 v when power is turned on. warning: the recommended operating conditions are require d in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating cond ition ranges. operation outside these ranges may adversely affect re liability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min max power supply voltage * 2 v cc 2.7 * 1 3.6 v normal operation assurance range v cc 1.8 3.6 v retains the ram state in stop mode a/d converter reference input voltage * 3 avr 0 av cc v normal operation assurance range lcd power supply voltage v1 to v3 v ss v cc v v1 to v3 pins (the optimum value is dependent on the lcd element in use.) operating temperature t a ? 40 + 85 c
mb90378 series 39 3. dc characteristics (v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?h? level input voltage v ih p10 to p17, p20 to p27, p30 to p37, p46, p47, p51 to p57, pc0 to pc7, pd0 to pd7 ? 0.7 v cc ? v cc + 0.3 v cmos input pins v ihs p00 to p07, p60 to p67, p70 to p77, p83 to p86, pa0 to pa7, pb0 to pb7, pe0 to pe7, pf0 to pf7, rst 0.8 v cc ? v cc + 0.3 v cmos hysteresis input pins v ihs5 p40 to p45 0.8 v cc ? v ss + 5.5 v 5 v tolerant cmos hysteresis input pins v ih5 p50, p82 0.7 v cc ? v ss + 5.5 v 5 v tolerant cmos input pins v ihsm p80, p81, p90 to p95 2.1 ? v ss + 5.5 v smbus input pins v ihm md0 to md2 v cc ? 0.3 ? v cc + 0.3 v mode pins ?l? level input voltage v il p10 to p17, p20 to p27, p30 to p37, p46, p47, p50 to p57, p82, pc0 to pc7, pd0 to pd7 ? v ss ? 0.3 ? 0.3 v cc v cmos input pins v ils p00 to p07, p40 to p45, p60 to p67, p70 to p77, p83 to p86, pa0 to pa7, pb0 to pb7, pe0 to pe7, pf0 to pf7, rst v ss ? 0.3 ? 0.2 v cc v cmos hysteresis input pins v ilsm p80, p81, p90 to p95 v ss ? 0.3 ? 0.8 v smbus input pins v ilm md0 to md2 v ss ? 0.3 ? v ss + 0.3 v mode pins open-drain output pin application voltage v d5 p40 to p45, p50, p80 to p82, p90 to p95 ? v ss ? 0.3 ? v ss + 5.5 v v d p46, pf0 to pf7 v ss ? 0.3 ? v cc + 0.3 v ?h? level output voltage v oh1 all port pins except p40 to p46, p50, p80 to p82, p90 to p95, pf0 to pf7 v cc = 3.0 v i oh1 = ? 4.0 ma v cc ? 0.5 ?? v ?l? level output voltage v ol1 all port pins except pf0 to pf7 i ol1 = 4.0 ma ?? 0.4 v v ol2 pf0 to pf7 i ol2 = 12.0 ma ?? 0.4 v
mb90378 series 40 (continued) parameter symbol pin name condition value unit remarks min typ max input leakage current (hi-z output leakage current) i il all input pins v cc = 3.3 v, v ss < v i < v cc ? 5 ? 5 a open-drain output leakage current i leak p40 to p46, p50, p80 to p82, p90 to p95, pf0 to pf7 ??? 5 a power supply current* i cc v cc v cc = 3.3 v, internal operation at 20 mhz ? 56 68 ma i ccs v cc = 3.3 v, internal operation at 20 mhz, in sleep mode ? 23 30 ma i ccl v cc = 3.3 v, external 32 khz, internal operation at 8 khz, in sub-clock mode, t a = + 25 c ? 23 80 a i ccls v cc = 3.3 v, external 32 khz, internal operation at 8 khz, in sub-clock sleep mode, t a = + 25 c ? 10 50 a i ccwat v cc = 3.3 v, external 32 khz, internal operation at 8 khz, in watch mode, t a = + 25 c ? 1.5 30 a power supply current* i cct v cc v cc = 3.3 v, internal operation at 20 mhz, in timebase timer mode ? 2.0 3 ma i cch v cc = 3.3 v, in stop mode, t a = + 25 c ? 120 a input capacitance c in all input pins except v cc , av cc , v ss , av ss ?? 10 80 pf
mb90378 series 41 (continued) * : the current value is preliminary value and may be subject to change for enhanc ed characteristics without previous notice. the power supply current is measured with an external clock. parameter symbol pin name condition value unit remarks min typ max lcd divided resistance r lcd ? between v cc and v3 at v cc = 3.3 v 100 200 400 k ? between v3 and v2 between v2 and v1 between v1 and v ss at v cc = 3.3 v 50 100 200 com0 to com3 output impedance r vcom com0 to com3 v1 to v3 = 3.3 v ?? 5k ? seg0 to seg8 output impedance r vseg seg0 to seg8 ?? 5k ? lcd leakage current l lcdl v1 to v3, com0 to com3, seg0 to seg8 ??? 1 a pull-up resistance r up p00 to p07,p10 to p17, p20 to p27,p30 to p37, rst ? 25 50 100 k ? pull-down resistance r down md2 ? 25 50 100 k ? mb90v378 only
mb90378 series 42 4. ac characteristics (1) clock timings (v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ max clock frequency f ch x0, x1 ? 3 ? 16 mhz 1/2 ( when pll stops ) when using an oscillation circuit 4 ? 16 mhz pll 1 when using an oscillation circuit 4 ? 10 mhz pll 2 when using an oscillation circuit 4 ? 6.67 mhz pll 3 when using an oscillation circuit 4 ? 5mhz pll 4 when using an oscillation circuit 3 ? 32 mhz 1/2 ( when pll stops ) when using an external clock 4 ? 20 mhz pll 1 when using an external clock 4 ? 10 mhz pll 2 when using an external clock 4 ? 6.67 mhz pll 3 when using an external clock 4 ? 5mhz pll 4 when using an external clock f cl x0a, x1a ?? 32.768 ? khz clock cycle time t hcyl x0, x1 ? 31.25 ? 333 ns t lcyl x0a, x1a ?? 30.5 ? s frequency fluctuation rate locked* ? f ???? 5% input clock pulse width p wh p wl x0 ? 5 ?? ns recommend duty ratio of 30% to 70% p whl p wll x0a ?? 15.2 ? s recommend duty ratio of 30% to 70% input clock rise/fall time t cr t cf x0 ??? 5ns external clock operation internal operating clock frequency f cp ?? 1.5 ? 20 mhz main clock operation f lcp ??? 8.192 ? khz sub-clock operation internal operating clock cycle time t cp ?? 50 ? 666 ns main clock operation t lcp ??? 122.1 ? s sub-clock operation
mb90378 series 43 t hcyl p wh t cf p wl t cr x 0 0.8 v cc 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc x 0a p whl t cf t lcyl t cr p wll 0.8 v cc 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc ? x0, x1 clock timing ? x0a, x1a clock timing
mb90378 series 44 power supply voltage v cc (v) machine clock f cp (mhz) 1.5 3 4 16 20 3.6 3.0 2.7 operation guarantee range of pll normal operation guarantee range guaranteed oscillation frequency range ? pll operation guarantee range relationship between machine clo ck frequency and power supply voltage relationship between external cloc k frequency and machine clock frequency machine clock f cp (mhz) external clock f c (mhz)* 3 6.67 41624 20 16 12 8 4 1.5 812 32 1 4 3 2 guaranteed oscillation frequency range 510 20 1 2 (pll off) * : when using a crystal oscillator or a ceramic oscilla tor, the maximum oscillation clock frequency is 16 mhz.
mb90378 series 45 the ac ratings are measured for the follo wing measurement reference voltages : hysteresis input pin cmos input pin smbus input pin output pin 0.8 v cc 0.2 v cc 0.7 v cc 0.3 v cc 2.1 v 0.8 v 2.4 v 0.8 v ? input signal waveform ? output signal waveform
mb90378 series 46 (2) reset input timing (v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : oscillation time of oscillator is the time to reach to 90% of the oscillation amplitude from stand still. in the crystal oscillator, the oscillation time is between several ms to t ens of ms. in far/ceramic oscillator, the oscillation time is between hundreds of s to several ms. in the external clock, the oscillation time is 0 ms. note : t cp is the internal operating clock cycle time. refer to ?(1) clock timings? rating for t cp . parameter symbol pin name condition value unit remarks min max reset input time t rstl rst ? 16 t cp ? ns normal operation oscillation time of oscillator* + 16 t cp ? ms in stop mode and sub-clock mode t rstl 0.2 v cc 0.2 v cc 16 t cp rst x0 90% of oscillation amplitude instruction execution oscillation stabilization time oscillation time of oscillator i nternal operation c lock internal reset ? in stop mode
mb90378 series 47 (3) power-on reset (v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : v cc must be kept lower than 0.2 v before power-on. notes : ? the above values are used for causing a power-on reset. some registers in the device are initialized only upon a power-on reset. to initialize these registers, turn on the power supply using the above values. ? make sure that power supply rises within the sele cted oscillation stabilization time. if the power supply voltage needs to be varied in the course of operation, a smooth voltage rise is recommended. parameter symbol pin name condition value unit remarks min max power supply rise time t r v cc * ? ? 50 ms power supply cut-off time t off v cc *1 ? ms due to repeated operations t off t r 2.2 v 0.2 v 0.2 v 0.2 v v cc ram data hold v cc 1.8 v v ss sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, it is recommended to raise the voltage smoothly to suppress fl uctuations as shown below. in this case, change the supply voltage with the pll clock not used. if the voltage drop is 1 v or fewer per second, however, you can use the pll clock. it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower.
mb90378 series 48 (4) uart1 to uart3 (v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? these are ac ratings in the clk synchronous mode. ? c l is the load capacitance value co nnected to pins while testing. ? t cp is the internal operating clock cycle time . refer to ?(1) clock timings? rating for t cp . parameter symbol pin name condition value unit remarks min max serial clock cycle time t scyc uck1 to uck3 c l = 80 pf + 1 ttl for an output pin of internal shift clock mode 4 t cp ? ns uck uo delay time t slov uck1 to uck3, uo1 to uo3 ? 80 80 ns valid ui uck t ivsh uck1 to uck3, ui1 to ui3 100 ? ns uck valid ui hold time t shix uck1 to uck3, ui1 to ui3 t cp ? ns serial clock ?h? pulse width t shsl uck1 to uck3 c l = 80 pf + 1 ttl for an output pin of external shift clock mode 4 t cp ? ns serial clock ?l? pulse width t slsh uck1 to uck3 4 t cp ? ns uck uo delay time t slov uck1 to uck3, uo1 to uo3 ? 150 ns valid ui uck t ivsh uck1 to uck3, ui1 to ui3 60 ? ns uck valid ui hold time t shix uck1 to uck3, ui1 to ui3 60 ? ns
mb90378 series 49 t scyc t slov 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t shix t ivsh uck uo ui ? internal shift clock mode t shix t slsh 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc t slov 2.4 v 0.8 v t shsl 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t ivsh uck uo ui ? internal shift clock mode
mb90378 series 50 (5) resources input timing (v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp is the internal operating clock cycle time. refer to ?(1) clock timings? rating for t cp . (6) trigger input timing (v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp is the internal operating clock cycle time. refer to ?(1) clock timings? rating for t cp . parameter symbol pin name condition value unit remarks min max timer input pulse width t tiwh t tiwl tin1 to tin6 ? 4 t cp ? ns parameter symbol pin name condition value unit remarks min max input pulse width t trgh t trgl adtg, int0 to int7, eei0 to eei15, ksi0 to ksi7 ? 5 t cp ? ns normal operation 1 ? s stop mode 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl tin1 to tin6 t trgh eei0 to eei15 int0 to int7 ksi0 to ksi7 adtg 0.8 v cc 0.8 v cc 0.2 v cc 0.2 v cc t trgl 0.7 v cc 0.7 v cc 0.3 v cc 0.3 v cc t trgl t trgh
mb90378 series 51 (7) i 2 c / multi-address i 2 c timing (v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? t cp is the internal operating clock cycle time . refer to ?(1) clock timings? rating for t cp . ? m is the setting bit of shift clock oscillation defined in the ?iccr register (cs4, cs3)? and ?mccr register (cs4, cs3)?. please refer to the mb 90378 series h/w manual for details. ? n is the setting bit of shift clock oscillation defined in the ?iccr register (cs2 to cs0)? and ?mccr register (cs2 to cs0)?. please refer to the mb90378 series h/w manual for details. ? t dosu is shown in the interrupt time is longer than the ?l? width of scl. ? sda and scl output value is specified on cond ition that the rise/fall time is ?0 ns?. *1 : at the stop condition or transferring of next byte. *2 : after setting register bit ibcrh : scc at restart. parameter symbol pin name value unit remarks min max start condition output t sta scl, sda t cp (m x n/2 ? 1) ? 20 t cp (m x n/2 ? 1) + 20 ns master mode stop condition output t sto scl, sda t cp (m x n/2 + 3) - 20 t cp (m x n/2 + 3) + 20 ns master mode start condition detect t sta scl, sda t cp + 40 ? ns stop condition detect t sto scl, sda t cp + 40 ? ns restart condition output t stasu scl, sda t cp (m x n/2 + 3) ? 20 t cp (m x n/2 + 3) + 20 ns master mode restart condition detect t stasu scl, sda t cp + 40 ? ns scl output ?l? width t low scl t cp x m x n/2 ? 20 t cp x m x n/2 + 20 ns master mode scl output ?h? width t high scl t cp (m x n/2 + 2) ? 20 t cp (m x n/2 + 2) + 20 ns master mode sda output delay t do sda t cp x 3 ? 20 t cp x 3 + 20 ns sda output setup time after interrupt t dosu sda t cp x m x n/2 ? 20 ? ns *1 t cp x 4 ? 20 ? ns *2 scl input ?l? pulse t low scl t cp x 3 + 40 ? ns scl input ?h? pulse t high scl t cp + 40 ? ns sda output setup time t su sda 40 ? ns sda hold time t ho sda 0 ? ns
mb90378 series 52 sda scl t su t stasu t sta t low t ho t do 1 ack 9 t do t ho t dosu ? data transmit (master/slave) ? data receive (master/slave) sda scl 67 8 9 ack t su t ho t do t do t dosu t sto t low t high
mb90378 series 53 (8) ps/2 interface timing (v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = 0.0 v, t a = ? 40 c to + 85 c) note : t cp is the internal operating clock cycle time. refer to ?(1) clock timings? rating for t cp . parameter symbol pin name condition value unit remarks min typ max psck clock cycle time t pcyc psck0 to psck2, psda0 to psda2 ? 4 t cp ?? ns psck psda t plov psck0 to psck2, psda0 to psda2 transmission mode 2 t cp ?? ns valid psda psck t pivsh psck0 to psck2, psda0 to psda2 reception mode 1 t cp ?? ns psck valid psda hold time t phix psck0 to psck2, psda0 to psda2 1 t cp ?? ns psck clock ?h? pulse width t phsl psck0 to psck2, psda0 to psda2 ? 2 t cp ?? ns psck clock ?l? pulse width t plsh psck0 to psck2, psda0 to psda2 2 t cp ?? ns psck0 psck1 psck2 psda0 psda1 psda2 psda0 psda1 psda2 t phix t pcyc t plov t pivsh 0.8 v cc 0.8 v cc 0.2 v cc 0.8 v 2.4 v 0.8 v cc 0.2 v cc ? transmission mode ? reception mode
mb90378 series 54 (9) lpc timing (v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit remarks min typ max lclk cycle time t cycle ?? 30 ?? ns lclk high time t high ?? 12 ?? ns lclk low time t low ?? 12 ?? ns lclk 0.7 v cc 0.3 v cc t cycle t high t low ? lclk ac timing
mb90378 series 55 parameter symbol pin name condition value unit remarks min typ max output valid delay t val ?? 2 ? 12 ns float to active delay t on ?? 2 ?? ns active to float delay t off ???? 28 ns input setup time t s ?? 7 ?? ns input hold time t h ?? 0 ?? ns lclk output delay tri-state output 0.4 v cc t val t on t off ? lad, lframe , ga20 ac timing lclk input 0.4 v cc t s t h
mb90378 series 56 5. a/d converter electrical characteristics (2.7 v avr ? av ss , v cc = av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) *: the current when the a/d converter is not operating or the cpu is in stop mode (for v cc = av cc = avr = 3.0 v). parameter symbol pin name value unit remarks min typ max resolution ?? ? ? 10 bit total error ?? ? ? 3.0 lsb non-linear error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an11 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 5.5 lsb mv for mb90v378 av ss + 2.5 lsb for mb90f378 full-scale transition voltage v fst an0 to an11 avr ? 3.5 lsb avr ? 1.5 lsb avr + 0.5 lsb mv conversion time ?? 3.1 ?? s actual value is specified as a sum of values specified in adcr0 : ct1, ct0 and adcr0 : st1, st0. be sure that the setting value is greater than the min value sampling period ?? 2 ?? s actual value is specified in adcr0 : st1, st0 bits. be sure that the setting value is greater than the min value analog port input current i ain an0 to an11 ? 0.1 10 a analog input voltage v ain an0 to an11 av ss ? avr v reference voltage ? avr av ss + 2.7 ? av cc v power supply current i a av cc ? 1.4 6.4 ma i ah ?? 5 a* reference voltage supply current i r avr ? 94 300 a i rh ?? 5 a* offset between channels ? an0 to an11 ?? 4lsb
mb90378 series 57 6. a/d converter glossary resolution : analog changes that are identifiable with the a/d converter. linearity error : the deviation of the straight li ne connecting the zero trans ition point (?00 0000 0000? ? ?00 0000 0001?) with the full-scale transition point (?11 1111 1110? ? ?11 1111 1111?) from actual conversion characteristics. differential linearity error : the deviation of input vo ltage needed to change the outpu t code by 1 lsb from the theoretical value. total error : the total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scal e transition error and linearity error. (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h avrl avrh v nt 0.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb } actual conversion value (measured value) actual conversion value theoretical characteristics digital output analog input total error for digital output n = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb (theoretical value) = avr ? avss 1024 [v] v ot (theoretical value) = avss + 0.5 lsb [v] v fst (theoretical value) = avr ? 1.5 lsb [v] v nt : voltage at a transition of digital output from (n ? 1) to n total error
mb90378 series 58 (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h avrl avrh avrl avr h n + 1 n n ? 1 n ? 2 v ot ( measured value ) {1 lsb (n ? 1) + v ot } actual conversion value v fst (measured value) v nt (measured value) actual conversion value theoretical characteristics actual conversion value actual conversion value theoretical characteristics digital output digital output analog input analog input v nt (measured value) v (n + 1) t (measured value ) linearity error of digital output n v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] = differential linearity error of digital output n v ( n + 1 ) t ? v nt 1 lsb ? 1 [lsb] = v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at transition of digital output from ?000 h ? to ?001 h ? v fst : voltage at transition of digital output from ?3fe h ? to ?3ff h ? linearity error differential linearity error
mb90378 series 59 7. notes on using a/d converter ? about the external impedance of th e analog input and its sampling time a/d converter with sample and hold circuit. if the exte rnal impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sampling and hold capacitor is insufficient, adversely affecting a/d conversion precision. to satisfy the a/d conversion precision standard, cons ider the relationship between the external impedance and minimum sampling time and either adjust the re sistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. if the sampling time cannot be suffici ent, connect a capacitor of about 0.1 f to the analog input pin. about errors as |avr ? av ss | becomes smaller, values of relative errors grow larger. r c analog input circuit model analog input comparator during sampling : on r 1.9 k ? (max) c 25 pf (max) note : the values are reference values. mb90f378/v378 1 00 90 80 70 60 50 40 30 20 10 0 35 30 25 20 15 10 5 0 0 1 2 34 5 6 7 8 0 2 4 6 8 10 12 14 16 18 20 mb90f378/v378 mb90f378/v378 the relationship between the external impedance and minimum sampling time minimum sampling time ( s) minimum sampling time ( s) external impedance (k ? ) external impedance (k ? ) [external impedance = 0 k ? to 100 k ? ] [external impedance = 0 k ? to 20 k ? ]
mb90378 series 60 8. d/a electrical characteristics (v cc = av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : with load capacitance is 20 pf. 9. serial irq electrical characteristics (v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) 10. flash memory program/erase characteristics parameter symbol pin name condition value unit remarks min typ max resolution ?? ? ? 8 ? bit differential linearity error ?? ?? 0.9 lsb non-linearity error ?? ?? 1.5 lsb conversion time ?? ? 0.6 ? s* analog output impedance ?? 2.0 2.9 3.8 k ? power supply current i dvr av cc ?? 460 a i dvrs av cc ? 0.1 ? a d/a stops parameter symbol pin name condition value unit remarks min typ max ?h? level input voltage v ih ?? 0.7 v cc ? v cc v ?l? level input voltage v il ?? v ss ? 0.3 v cc v ?h? level output voltage v oh ?? v cc ? 0.5 ?? v ?l? level output voltage v ol ???? 0.4 v parameter condition value unit remarks min typ max sector erase time (4 kbytes sector) t a = + 25 c v cc = 3.0 v ? 0.2 0.5 s excludes 00 h programming prior to erasure sector erase time (16 kbytes sector) ? 0.5 7.5 s excludes 00 h programming prior to erasure chip erase time ? 4.6 ? s excludes 00 h programming prior to erasure byte (8-bit width) programing time ? 32 3,600 s except for the over head time of the system program/erase cycle ? 10,000 ?? cycle
mb90378 series 61 example characteristics (mb90f378) power supply current (continued) fcin = 16 mhz fcin = 10 mhz fcin = 8 mhz fcin = 4 mhz fcin = 2 mhz t a = + 25 [ c] i cc [ma] v cc [v] 50.0 40.0 30.0 20.0 10.0 0.0 2.0 2.5 3.0 3.5 4.0 fcin = 12 mhz t a = + 25 [ c] i ccs [ma] v cc [v] 18.0 14.0 10.0 2.0 0.0 2.0 2.5 3.0 3.5 4.0 fcin = 16 mhz fcin = 12 mhz fcin = 10 mhz fcin = 8 mhz fcin = 4 mhz fcin = 2 mhz 4.0 6.0 8.0 12.0 16.0 v cc [v] 2.5 2.0 1.5 1.0 0.5 0.0 2.5 3.0 3.5 4.0 t a = + 25 [ c] i cch [ a]
mb90378 series 62 (continued) t a = + 25 [ c] v cc ? v oh1 [v] i oh1 [ma] 0 ? 2 ? 4 ? 6 ? 8 ? 10 0.0 0.5 1.0 1.5 2.0 v cc = 2.5 [v] v cc = 3.0 [v] v cc = 3.5 [v] v cc = 4.0 [v] t a = + 25 [ c] v cc ? v oh2 [v] i oh2 [ma] 0 ? 2 ? 4 ? 6 ? 8 ? 10 0.0 0.1 0.3 0.4 0.7 v cc = 2.5 [v] v cc = 3.0 [v] v cc = 3.5 [v] v cc = 4.0 [v] 0.2 0.5 0.6 t a = + 25 [ c] v ol1 [v] i ol1 [ma] 0246810 0.0 0.2 0.4 0.6 0.8 v cc = 2.5 [v] v cc = 3.0 [v] v cc = 4.0 [v] v cc = 3.5 [v] t a = + 25 [ c] v ol2 [v] i ol2 [ma] 0246810 0.0 0.1 0.2 0.3 v cc = 2.5 [v] v cc = 3.0 [v] v cc = 3.5 [v] v cc = 4.0 [v]
mb90378 series 63 ordering information part number package remarks MB90F378PFF-GE1 144-pin plastic lqfp (fpt-144p-m12)
mb90378 series 64 package dimension 144-pin plastic lqfp (fpt-144p-m12) c 2003 fujitsu limited f144024s-c-3-3 .059 ? .004 +.008 ? 0.10 +0.20 1.50 details of "a" part 0~8 ? (mounting height) 0.600.15 (.024.006) 0.25(.010) (.004.002) 0.100.05 (stand off) 0.08(.003) 0.145 ? 0.03 +.002 ? .001 .006 +0.05 "a" .007.001 0.180.035 m 0.07(.003) 36 37 1 lead no. 0.40(.016) index 144 109 108 18.000.20(.709.008)sq sq 16.00 73 72 * .630 ? .004 +.016 ? 0.10 +0.40 dimensions in mm (inches). note: the values in parent heses are refe rence values . note 1) * : these dimensions include resin protrusion. resin protrusion is +0.25(.010)max(each side). note 2) pins width and pins thic kness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
mb90378 series fujitsu limited all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose of reference to show examples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any damages whatsoever arising out of the use of the information. any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use or exercise of any intellectual property right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or othe r right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as contemplated for general use, including without limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extremel y high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon syst em), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liable against you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design m easures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan. f0504 ? 2005 fujitsu limited printed in japan

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